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Espressif Systems /ESP32-S2 /PMS /CACHE_TAG_ACCESS_1

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Interpret as CACHE_TAG_ACCESS_1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PRO_I_TAG_RD_ACS)PRO_I_TAG_RD_ACS 0 (PRO_I_TAG_WR_ACS)PRO_I_TAG_WR_ACS 0 (PRO_D_TAG_RD_ACS)PRO_D_TAG_RD_ACS 0 (PRO_D_TAG_WR_ACS)PRO_D_TAG_WR_ACS

Description

Cache tag permission control register 1.

Fields

PRO_I_TAG_RD_ACS

Setting to 1 permits read access to Icache tag memory.
PRO_I_TAG_WR_ACS

Setting to 1 permits write access to Icache tag memory.
PRO_D_TAG_RD_ACS

Setting to 1 permits read access to Dcache tag memory.
PRO_D_TAG_WR_ACS

Setting to 1 permits write access to Dcache tag memory.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd